Tweak3D.net - How Bus Mastering Works

Posted: October 24, 2000
Written by: Tuan "Solace" Nguyen

DMA Mode Transfer (cont.)

The highest performing DMA type is called first party or Bus Mastering DMA. Peripheral devices, which support the Bus Mastering technology, have the ability to move data to and from system memory without intervention of the CPU or a third party DMA controller.

Bus Mastering allows data to be transferred much faster than PIO or third party DMA. This is because half as many bus cycles are needed. Both PIO and third party DMA require the CPU or DMA controller to alternately read a segment of data from one device (this can be the a peripheral device or system memory) and write it to the other device. Each data segment requires at least one bus cycle to be read and one bus cycle to be written. Bus mastering devices only require bus cycles when accessing system memory, so half as many bus cycles are needed. As a bonus, system memory can be accessed using high-speed transferring techniques such as page mode access.

Because of this, devices that support Bus Mastering can move data many times faster than either PIO or third party DMA. Bus Mastering controllers typically support Command Queuing and Scatter/Gather memory access, which greatly increase performance in multi-user environments like Windows NT/2000, UNIX/Linux and Novell.

DMA Transfers

A typical Bus Mastering controller would process an I/O command as follows:

The CPU creates a Command Block in system RAM and writes the address of this block into a register in the peripheral controller. The CPU can then perform other tasks. The peripheral controller will perform all remaining operations.

The Command Block contains parameters, specifying the type of operation, the amount of data and the location on the peripheral device. The Command Block may also contain pointers to a Scatter/Gather table and a Status Block. The Scatter/Gather Table describes a list of data segments to be read or written to sequential locations on the peripheral device. These data segments may be scattered in many different areas of system RAM. The Status Block is a place in system Ram for the peripheral controller to save status information concerning the successful or unsuccessful completion of the command.

The peripheral controller becomes the Bus Master (takes control of the system bus) and DMAs the Command Block and Scatter/Gather Table into its local memory.

When the peripheral controller is ready to transfer the data, it again becomes the Bus Master and DMAs the data to the areas specified by the Scatter/Gather table.

When the command is complete, the peripheral controller becomes the Bus Master and DMAs the Status Information into the proper RAM location.

The peripheral controller interrupts the CPU to tell the computer that the command has completed.

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